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ds1962/DS1963 1kbit/4kbit monetary i button tm ds1962/DS1963 preliminary 020698 1/22 special features ? 4096 bits of read/write nonvolatile memory (DS1963), 1024 bits with the ds1962 ? overdrive mode boosts communication speed to 142k bits per second ? 256bit scratchpad ensures integrity of data transfer ? memory partitioned into 256bit pages for packetizing data ? data integrity assured with strict read/write protocols ? four 32bit readonly non rollingover page write cycle counters (DS1963), three page write cycle counters with the ds1962 ? 32 factorypreset tamperdetect bits to indicate physical intrusion ? onchip 16bit crc generator for safeguarding data transfers ? operating temperature range from 40 c to +70 c ? over 10 years of data retention common i button features ? unique, factorylasered and tested 64bit registra- tion number (8bit family code + 48bit serial number + 8bit crc tester) assures absolute traceability because no two parts are alike ? multidrop controller for microlan tm ? digital identification and information by momentary contact ? chipbased data carrier compactly stores informa- tion ? can be accessed while affixed to object ? economically communicates to host with a single digi- tal signal at 16.3k bits per second ? standard 16 mm diameter and 1wire tm protocol ensure compatibility with i button device family ? button shape is selfaligning with cupshaped probes ? durable stainless steel case engraved with registra- tion number withstands harsh environments ? easily affixed with selfstick adhesive backing, latched by its flange, or locked with a ring pressed onto its rim ? presence detector acknowledges when reader first applies voltage ? meets ul#913 (4th edit.); intrinsically safe appara- tus, approved under entity concept for use in class i, division 1, group a, b, c and d locations (applica- tion pending) f5 microcan tm 18 51 000000fbc52b yyww 16.25 17.35 registered rr 5.89 ground data 0.36 0.51 ordering information ds1962lf5 f5 microcan DS1963lf5 f5 microcan examples of accessories ds9096p selfstick adhesive pad ds9101 multipurpose clip ds9093ra mounting lock ring ds9093f snapin fob ds9092 i button probe i button description the ds1962/DS1963 monetary i button (hereafter referred to as ds196x) is a rugged read/write data car- rier that acts as a localized database that can be easily accessed with minimal hardware. the nonvolatile memory offers a simple solution to storing and retrieving information pertaining to the object to which the i button is associated. data is transferred serially via the 1wire protocol which requires only a single data lead and a ground return.
ds1962/DS1963 020698 2/22 the scratchpad is an additional page that acts as a buffer when writing to memory. data is first written to the scratchpad where it can be read back. after the data has been verified, a copy scratchpad command will transfer the data to memory. this process insures data integrity when modifying the memory. a 48bit serial number is factory lasered into each ds196x to provide a guaran- teed unique identity which allows for absolute traceabil- ity. the durable microcan package is highly resistant to environmental hazards such as dirt, moisture, and shock. its compact coinshaped profile is selfaligning with mating receptacles, allowing the ds196x to be easily used by human operators. accessories permit the ds196x to be mounted on almost any surface including plastic key fobs, photoid badges and printed circuit boards. application the ds196x monetary i button can store encrypted data which represents money. the unique registration number, the page write cycle counters, crc generator and tamperdetect bits prevent unauthorized refilling of the purses. up to four independent change purses (DS1963; three purses with the ds1962) can be ran- domly accessed from the onchip directory. tamper detect bits report if the purses have experienced physi- cal tampering. each write cycle (amonetary transactiono) generates a unique number to audit the dispensing and refilling of the purses. a change purse can be decremented with less than 100 ms touch dwell time for rapid processing in crowded public facilities. overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the ds196x. the ds196x has four main data components: 1) 64bit lasered rom, 2) 256bit scratchpad, 3) 1024bit (ds1962) or 4096bit (DS1963) sram, and 4) three (ds1962) or four (DS1963) 32bit readonly page write cycle counters. the hierarchical structure of the 1wire protocol is shown in figure 2. each of these counters is associated with one of the 256bit memory pages. the three counters of the ds1962 are associated with pages 1 to 3; the four counters of the DS1963 are associated with pages 12 to 15. the con- tents of the counter is read together with the memory data using a special command. the bus master must first provide one of the six rom function commands, 1) read rom, 2) match rom, 3) search rom, 4) skip rom, 5) overdriveskip rom or 6) overdrivematch rom. upon completion of an overdrive rom command byte executed at standard speed, the device will enter overdrive mode where all subsequent communication occurs at a higher speed. the protocol required for these rom function commands is described in figure 9. after a rom function command is successfully executed, the memory functions become accessible and the master may provide any one of the five memory function commands. the protocol for these memory function commands is described in figure 7. all data is read and written least significant bit first. parasite power the block diagram (figure 1) shows the parasitepow- ered circuitry. this circuitry astealso power whenever the i/o input is high. i/o will provide sufficient power as long as the specified timing and voltage requirements are met. the advantages of parasite power are twofold: 1) by parasiting off this input, lithium is conserved and 2) if the lithium is exhausted for any reason, the rom may still be read normally. 64bit lasered rom each ds196x contains a unique rom code that is 64 bits long. the first eight bits are a 1wire family code. the next 48 bits are a unique serial number. the last eight bits are a crc of the first 56 bits. (see figure 3). the 1wire crc is generated using a polynomial gen- erator consisting of a shift register and xor gates as shown in figure 4. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the dallas 1wire cyclic redundancy check is available in the book of ds19xx i button standards. the shift register bits are initialized to zero. then start- ing with the least significant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, then the serial number is entered. after the 48th bit of the serial number has been entered, the shift register contains the crc value. shifting in the eight bits of crc should return the shift register to all zeros.
ds1962/DS1963 020698 3/22 ds196x block diagram figure 1 64-bit lasered rom 1wire function control memory function control 256bit scratchpad data parasitepowered circuitry lid contact 3v lithium memory 4096bit (DS1963) 1024bit (ds1962) sram (256bit pages) page write cycle counters memory the memory map in figure 5 shows a 32byte page called the scratchpad and additional 32 byte pages called memory. the ds1962 contains pages 0 through 3 which make up the 1024bit sram. the DS1963 con- tains pages 0 through 15 which make up the 4096bit sram. the scratchpad is an additional page that acts as a buffer when writing to memory. address registers and transfer status because of the serial data transfer, the ds196x employs three address registers, called ta1, ta2 and e/s (figure 6). registers ta1 and ta2 must be loaded with the target address to which the data will be written or from which data will be sent to the master upon a read command. register e/s acts like a byte counter and transfer status register. it is used to verify data integrity with write commands. therefore, the master only has read access to this register. the lower five bits of the e/s register indicate the address of the last byte that has been written to the scratchpad. this address is called ending offset. bit 5 of the e/s register, called pf or apartial byte flag,o is set if the number of data bits sent by the master is not an integer multiple of 8. bit 6 has no function; it always reads 0. note that the lowest five bits of the target address also determine the address within the scratchpad, where intermediate storage of data will begin. this address is called byte offset. if the target address (ta1) for a write command is 03ch for exam- ple, then the scratchpad will store incoming data begin- ning at the byte offset 1ch and will be full after only four bytes. the corresponding ending offset in this example is 1fh. for best economy of speed and efficiency, the target address for writing should point to the beginning of a new page, i.e., the byte offset will be 0. thus the full 32 byte capacity of the scratchpad is available, resulting also in the ending offset of 1fh. however, it is possible to write one or several contiguous bytes somewhere within a page. the ending offset together with the partial flag support the master checking the data integrity after a write command. the highest valued bit of the e/s reg- ister, called aa or authorization accepted, acts as a flag to indicate that the data stored in the scratchpad has already been copied to the target memory address. writing data to the scratchpad clears this flag.
ds1962/DS1963 020698 4/22 hierarchcal structure for 1wire protocol figure 2 1wire rom function commands (see figure 9) ds196x specific memory function commands (see figure 7) command level: available commands: data field affected: read rom match rom search rom skip rom 64bit rom 64bit rom 64bit rom n/a write scratchpad 256bit scratchpad read scratchpad copy scratchpad read memory 256bit scratchpad data memory, write cycle counter bus master 1wire bus other devices ds196x overdrive skip rom overdrive match rom n/a 64bit rom read memory + counter data memory data memory, write cycle counter, tamperdetect bits 64bit lasered rom figure 3 8bit crc code 48bit serial number 8bit family code msb lsb msb lsb msb lsb msb lsb (18h = ds1962, 1ah = DS1963) 1wire crc generator figure 4 1st stage 2nd stage 3rd stage 4th stage 5th stage 6th stage 7th stage 8th stage x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 polynomial = x 8 + x 5 + x 4 + 1 xor xor xor input
ds1962/DS1963 020698 5/22 writing with verification to write data to the ds196x, the scratchpad has to be used as intermediate storage. first the master issues the write scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. under certain conditions (see write scratchpad command) the master will receive an inverted crc16 of the command, address and data at the end of the write scratchpad command sequence. knowing this crc value, the master can compare it to the value it has calculated itself to decide if the commu- nication was successful and proceed to the copy scratchpad command. if the master could not receive the crc16, it has to send the read scratchpad com- mand to read back the scratchpad to verify data integ- rity. as preamble to the scratchpad data, the ds196x repeats the target address ta1 and ta2 and sends the contents of the e/s register. if the pf flag is set, data did not arrive correctly in the scratchpad. the master does not need to continue reading; it can start a new trial to write data to the scratchpad. similarly, a set aa flag indi- cates that the write command was not recognized by the i button. if everything went correctly, both flags are cleared and the ending offset indicates the address of the last byte written to the scratchpad. now the master can continue reading and verifying every data byte. after the master has verified the data, it has to send the copy scratchpad command. this command must be followed exactly by the data of the three address regis- ters ta1, ta2 and e/s. the master may obtain the con- tents of these registers by reading the scratchpad or derive it from the target address and the amount of data to be written. as soon as the ds196x has received these bytes correctly, it will copy the data to the requested location beginning at the target address. memory function commands the amemory function flow charto (figure 7) describes the protocols necessary for accessing the memory. an example follows the flowchart. the communication between master and ds196x takes place either at regu- lar speed (default, od = 0) or at overdrive speed (od = 1). if not explicitly set into the overdrive mode the ds196x assumes regular speed. write scratchpad command [0fh] after issuing the write scratchpad command, the master must first provide the 2byte target address, followed by the data to be written to the scratchpad. the data will be written to the scratchpad starting at the byte offset (t4:t0). the ending offset (e4: e0) will be the byte offset at which the master stops writing data. only full data bytes are accepted. if the last data byte is incomplete its content will be ignored and the partial byte flag pf will be set. when executing the write scratchpad command the crc generator inside the ds196x (see figure 12) cal- culates a crc over the entire data stream, starting at the command code and ending at the last data byte sent by the master. this crc is generated using the crc16 polynomial by first clearing the crc generator and then shifting in the command code (0fh) of the write scratchpad command, the target addresses ta1 and ta2 as supplied by the master and all the data bytes. the master may end the write scratchpad command at any time. however, if the ending offset is 1 1111b, the master may send 16 read time slots and will receive the crc generated by the ds196x. the memory address range of the ds1962 is 0000h to 007fh and 0000h to 01ffh for the DS1963, respec- tively. if the bus master sends a target address higher than this, the internal circuitry of the chip will set the nine (ds1962) or seven (DS1963) most significant address bits to zero as they are shifted into the internal address register. the read scratchpad command will reveal the target address as it will be used by the ds196x. the master will identify such address modifications by comparing the target address read back to the target address transmitted. if the master does not read the scratchpad, a subsequent copy scratchpad command will not work since the most significant bits of the target address the master sends will not match the value the ds196x expects. read scratchpad command [aah] this command is used to verify scratchpad data and tar- get address. after issuing the read scratchpad com- mand, the master begins reading. the first two bytes will be the target address. the next byte will be the ending offset/data status byte (e/s) followed by the scratchpad data beginning at the byte offset (t4: t0). the master may read data until the end of the scratchpad after which the data read will be all logic 1's. copy scratchpad [5ah] this command is used to copy data from the scratchpad to memory. after issuing the copy scratchpad com- mand, the master must provide a 3byte authorization
ds1962/DS1963 020698 6/22 pattern which can be obtained by reading the scratch- pad for verification. this pattern must exactly match the data contained in the three address registers (ta1, ta2, e/s, in that order). if the pattern matches, the aa (authorization accepted) flag will be set and the copy will begin. a pattern of alternating 1's and 0's will be transmitted after the data has been copied until a reset pulse is issued by the master. any attempt to reset the part will be ignored while the copy is in progress. copy typically takes 30 m s. the data to be copied is determined by the three address registers. the scratchpad data from the begin- ning offset through the ending offset, will be copied to memory, starting at the target address. anywhere from 1 to 32 bytes may be copied to memory with this com- mand. the aa flag will be cleared only by executing a write scratchpad command. ds196x memory map figure 5 32byte intermediate storage scratchpad page 0 page 1 page 2 32byte final storage nv ram 001fh 003fh 005fh page 3 007fh page 4 final storage nv ram (DS1963 only) 017fh page 12 page 13 page 14 32byte final storage nv ram (DS1963 only) 019fh 01bfh 01dfh page 15 01ffh 0000h to 0020h to 0040h to address 0060h to 0080h to 0180h to 01a0h to 01c0h to 01e0h to 32byte final storage nv ram 32byte final storage nv ram 32byte final storage nv ram 32byte final storage nv ram (DS1963 only) 32byte final storage nv ram (DS1963 only) 32byte final storage nv ram (DS1963 only) to page 11 ds1962 DS1963 with page 1 with page 12 with page 2 with page 13 with page 3 with page 14 with page 15 (n/a) counter 1 counter 2 counter 3 counter 4 nonmemory mapped writecycle counters (accessible through a special read command)
ds1962/DS1963 020698 7/22 address registers figure 6 target address (ta1) target address (ta2) ending address with data status (e/s) (read only) t7 t6 t5 t4 t3 t2 t1 t0 t15 t14 t13 t12 t11 t10 t9 t8 aa 1) pf e4 e3 e2 e1 e0 1) this bit will always be 0. read memory [f0h] the read memory command may be used to read the entire memory. after issuing the command, the master must provide the 2byte target address. after the two bytes, the master reads data beginning from the target address and may continue until the end of memory, at which point logic 1's will be read. it is important to realize that the target address registers will contain the address provided. the ending offset/data status byte is unaf- fected. the hardware of the ds196x provides a means to accomplish errorfree writing to the memory section. to safeguard reading data in the 1wire environment and to simultaneously speed up data transfers, it is recom- mended to packetize data into data packets of the size of one memory page each. such a packet would typi- cally store a 16bit crc with each page of data to insure rapid, errorfree data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (see the book of ds19xx i button standards, chapter 7 for the recommended file struc- ture.) read memory + counter [a5h] the read memory + counter command is used to read memory data together with the write cycle counter associated with the addressed page of data memory. the additional information is transmitted by the ds196x as the end of a memory page is encountered. following the current value of the page write cycle counter the ds196x transmits 32 tamperdetect bits and a 16bit crc generated by the ds196x. the tamperdetect bits are factorypreset to 55555555h and locked. tam- pering with the device will change this data pattern. after having sent the command code of the read memory + counter command, the bus master sends a twobyte address (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. with the subsequent read data time slots the master receives data from the ds196x starting at the initial address and continuing until the end of a 32byte page is reached. at that point the bus master will send 80 additional read data time slots and receive the contents of the 32bit write cycle counter associated with the addressed page, the status of the 32 tamperdetect bits and a 16bit crc. with subsequent read data time slots the master will receive data starting at the begin- ning of the next page followed again by the contents of the page write cycle counter, tamperdetect bits and crc for that page. this sequence will continue until the final page and its accompanying data is read by the bus master. when applying the read memory + counter command to a page that does not have a page write cycle counter associated, the the master will read ffffffffh intead of a valid cycle count. with the initial pass through the read memory + counter flow chart the 16bit crc value is the result of shifting the command byte into the cleared crc gener- ator, followed by the two address bytes, the contents of the data memory, the write page cycle counter and the tamperdetect bits. subsequent passes through the read memory + counter flow chart will generate a 16bit crc that is the result of clearing the crc gener- ator and then shifting in the contents of the data memory page, its associated page write cycle counter and tam- perdetect bits. after the 16bit crc of the last page is read, the bus master will receive logical 1's from the ds196x until a reset pulse is issued. the read memory + counter command sequence can be ended at any point by issuing a reset pulse.
ds1962/DS1963 020698 8/22 memory function flow chart figure 7 aah read scratchpad ? bus master rx ta1 (t7:t0) bus master rx ta2 (t15:t8) ds196x sets scratchpad offset=(t4:t0) master rx ending offset with status (e/s) bus master tx reset ? scratch pad offset= 11111b ? bus master rx a1os y n y master tx memory function command 0fh write scratchpad ? n bus master tx ta1 (t7:t0) bus master tx ta2 (t15:t8) ds196x sets scratchpad offset = (t4:t0) and clears (pf, aa) master tx data byte to scratchpad offset ds196x sets (e4:e0) = scratchpad offset bus master tx reset ? bus master tx reset ? ds196x increments scratchpad offset partial byte written ? bus master rx a1os bus master tx reset ? pf = 1 y y n n y y n y n y from rom functions flow chart (figure 9) 1) 1) 1) 1) 2) bus master rx crc16 of command, address, data n 2) 2) 1) 1) ds196x increments scratchpad offset master rx data byte from scratchpad offset 1) n 2) 1) 1) 1) 1) y to figure 7 second part from figure 7 second part to rom functions flow chart (figure 9) 1) to be transmitted or received at overdrive speed if od = 1 2) reset pulse to be transmitted at overdrive speed if od = 1 reset pulse to be transmitted at regular speed if od = 0 or if the ds196x is to be reset from overdrive speed to regular speed scratch pad offset= 11111b ?
ds1962/DS1963 020698 9/22 memory function flow chart figure 7 cont'd n 5ah copy scratchpad ? n bus master tx ta1 (t7:t0) y 1) to figure 7 1) to be transmitted or received at overdrive speed if od = 1 2) reset pulse to be transmitted at overdrive speed if od = 1 reset pulse to be transmitted at regular speed if od = 0 or if the ds196x is to be reset from overdrive speed to regular speed bus master tx ta2 (t15:t8) 1) bus master tx e/s byte 1) au thori zation code match y aa = 1 ds196x copies scratchpad data to memory from figure 7 first part third part f0h read memory ? n bus master tx ta1 (t7:t0) y 1) bus master tx ta2 (t15:t8) 1) ds196x sets memory address = (t15:t0) 1) copying finished ? n y ds196x tx a0o bus master tx reset ? ds196x tx a1o bus master tx reset ? n bus master tx reset ? bus master rx a1os n 1) 2) 1) 2) 2) 1) n y 1) to figure 7 from figure 7 third part first part master rx data byte from memory address ds196x increments address counter bus master tx reset ? n end of memory ? y bus master rx a1os bus master rx a1os y y 2) n 1) y
ds1962/DS1963 020698 10/22 memory function flow chart figure 7 cont'd a5h read memory + counter ? n bus master tx ta1 (t7:t0) ds196x sets memory address = (t15:t0) legend: decision made by the master decision made by ds196x bus master tx reset 1) from figure 7 second part bus master tx ta2 (t15:t8) 1) bus master tx reset ? end of page ? bus master rx writecycle counter of memory page 1) bus master rx tamperdetect bytes 1) bus master rx crc 16 of command, address, data, counter, tamperdetect bytes (1st pass) crc 16 of data, counter, tamper detect bytes (subsequent passes) crc correct ? end of memory ? bus master tx reset ? bus master rx 1's y y y n 2) 1) ds196x increments address counter bus master tx reset ? 2) n y n y 2) n to figure 7 second part 1) y n n 2) y bus master rx data from memory 1) 1) to be transmitted or received at overdrive speed if od = 1 2) reset pulse to be transmitted at overdrive speed if od = 1 reset pulse to be transmitted at regular speed if od = 0 or if the ds196x is to be reset from overdrive speed to regular speed
ds1962/DS1963 020698 11/22 memory function example (DS1963) example: write two data bytes to memory location 0026 and 0027. read entire memory. master mode data (lsb first) comments tx reset reset pulse (480960 m s) rx presence presence pulse tx cch issue askip romo command tx 0fh issue awrite scratchpado command tx 26h ta1, beginning offset=26h tx 00h ta2, address=00 26h tx <2 data bytes> write 2 bytes of data to scratchpad tx reset reset pulse rx presence presence pulse tx cch issue askip romo command tx aah issue aread scratchpado command rx 26h read ta1, beginning offset=26h rx 00h read ta2, address=00 26h rx 07h read e/s, ending offset=7h, flags=0h rx <2 data bytes> read scratchpad data and verify tx reset reset pulse rx presence presence pulse tx cch issue askip romo command tx 5ah issue acopy scratchpado command tx 26h ta1 tx 00h ta2 authorization code tx 07h e/s tx reset reset pulse rx presence presence pulse tx cch issue askip romo command tx f0h issue aread memoryo command tx 00h ta1, beginning offset=0 tx 00h ta2, address=00 00h rx <512 bytes> read entire memory tx reset reset pulse rx presence presence pulse, done
ds1962/DS1963 020698 12/22 memory function example (ds1962) update purse file in page 1: read memory + counter, write scratchpad, copy scratchpad. master mode data (lsb first) comments tx reset reset pulse (480960 m s) rx presence presence pulse tx cch issue askip romo command tx a5h issue aread memory + countero command tx 20h ta1, beginning offset=20h tx 00h ta2, address=00 20h rx <32 data bytes> read 32 bytes of data rx <4 data bytes> read write cycle counter of page 1 rx <4 data bytes> read tamper detect bytes of device rx <2 data bytes> read (inverted) crc16 tx reset reset pulse rx presence presence pulse tx cch issue askip romo command tx 0fh issue awrite scratchpado command tx 20h ta1, beginning offset=20h tx 00h ta2, address=00 20h tx <32 data bytes> write 32 bytes of data to scratchpad rx <2 data bytes> read (inverted) crc16 tx reset reset pulse rx presence presence pulse tx cch issue askip romo command tx 5ah issue acopy scratchpado command tx 20h ta1 tx 00h ta2 authorization code tx 1fh e/s rx <1 data byte> read copy scratchpad response tx reset reset pulse rx presence presence pulse, done
ds1962/DS1963 020698 13/22 hardware configuration figure 8 v pup ds196x 1wire port r x t x 100 ohm mosfet 5 k w typ. r x t x r x = receive t x = transmit 5 m a typ. bus master data open drain port pin 1wire bus system the 1wire bus is a system which has a single bus mas- ter and one or more slaves. in all instances the ds196x is a slave device. the bus master is typically a micro- controller. the discussion of this bus system is broken down into three topics: hardware configuration, transac- tion sequence, and 1wire signaling (signal types and timing). a 1wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. for a more detailed protocol description, refer to chapter 4 of the book of ds19xx i button standards. hardware configuration the 1wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1wire bus must have open drain or 3state outputs. the 1wire port of the ds196x is open drain with an internal circuit equivalent to that shown in figure 8. a multidrop bus consists of a 1wire bus with multiple slaves attached. at regular speed the 1wire bus has a maximum data rate of 16.3k bits per second. the speed can be boosted to 142k bits per second by activating the overdrive mode. the 1wire bus requires a pullup resistor of approximately 5 k w . the idle state for the 1wire bus is high. if for any rea- son a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16 m s (overdrive speed) or more than 120 m s (regular speed), one or more devices on the bus may be reset. transaction sequence the protocol for accessing the ds196x via the 1wire port is as follows: ? initialization ? rom function command ? memory function command ? transaction/data initialization all transactions on the 1wire bus begin with an initial- ization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds196x is on the bus and is ready to operate. for more details, see the a1wire signalingo section. rom function commands once the bus master has detected a presence, it can issue one of the six rom function commands. all rom function commands are eight bits long. a list of these commands follows (refer to flowchart in figure 9): read rom [33h] this command allows the bus master to read the ds196x's 8bit family code, unique 48bit serial num- ber, and 8bit crc. this command can only be used if there is a single ds196x on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wiredand result). the resultant family code and 48bit serial number will result in a mis- match of the crc.
ds1962/DS1963 020698 14/22 match rom [55h] the match rom command, followed by a 64bit rom sequence, allows the bus master to address a specific ds196x on a multidrop bus. only the ds196x that exactly matches the 64bit rom sequence will respond to the following memory function command. all slaves that do not match the 64bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus. skip rom [cch] this command can save time in a single drop bus sys- tem by allowing the bus master to access the memory functions without providing the 64bit rom code. if more than one slave is present on the bus and a read command is issued following the skip rom command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wiredand result). search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1wire bus or their 64bit rom codes. the search rom com- mand allows the bus master to use a process of elimina- tion to identify the 64bit rom codes of all slave devices on the bus. the search rom process is the repetition of a simple 3step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple, 3step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and their rom codes may be identified by additional passes. see chapter 5 of the book of ds19xx i button standards for a comprehensive discussion of a search rom, including an actual example. overdrive skip rom [3ch] on a singledrop bus this command can save time by allowing the bus master to access the memory functions without providing the 64bit rom code. unlike the nor- mal skip rom command the overdrive skip rom sets the ds196x in the overdrive mode (od = 1). all com- munication following this command has to occur at overdrive speed until a reset pulse of minimum 480 m s duration resets all devices on the bus to regular speed (od = 0). when issued on a multidrop bus this command will set all overdrivesupporting devices into overdrive mode. to subsequently address a specific overdrivesupport- ing device, a reset pulse at overdrive speed has to be issued followed by a match rom or search rom com- mand sequence. this will speed up the time for the search process. if more than one slave supporting overdrive is present on the bus and the overdrive skip rom command is followed by a read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wireand result). overdrive match rom [69h] the overdrive match rom command, followed by a 64bit rom sequence transmitted at overdrive speed, allows the bus master to address a specific ds196x on a multidrop bus and to simultaneously set it in overdrive mode. only the ds196x that exactly matches the 64bit rom sequence will respond to the subsequent memory function command. slaves already in over- drive mode from a previous overdrive skip or match command will remain in overdrive mode. all other slaves that do not match the 64bit rom sequence or do not support overdrive will return to or remain at regu- lar speed and wait for a reset pulse of minimum 480 m s duration. the overdrive match rom command can be used with a single or multiple devices on the bus.
ds1962/DS1963 020698 15/22 rom functions flow chart figure 9 (first part) n y y y ds196x tx presence pulse 33h read rom command ? 55h match rom command ? f0h search rom command ? cch skip rom command ? ds196x tx family code 1 byte bit 0 match ? bit 0 match ? bit 1 match ? bit 1 match ? bit 63 match ? bit 63 match ? ds196x tx serial number 6 bytes ds196x tx crc byte n nn y y y nn y n n y y y ds196x tx bit 0 ds196x tx bit 0 ds196x tx bit 1 ds196x tx bit 1 ds196x tx bit 63 ds196x tx bit 63 master tx bit 1 master tx bit 0 master tx bit 0 master tx bit 1 master tx bit 63 master tx bit 63 master tx reset pulse master tx rom function command n n short reset pulse ? od=0 n y 1) to be transmitted or received at overdrive speed if od=1 2) the presence pulse will be short if od=1 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 2) from figure 9 second part to figure 9 second part to figure 9 second part from figure 9 second part 1) from memory funcitons flow chart (figure 7) to memory functions flow chart (figure 7)
ds1962/DS1963 020698 16/22 rom functions flow chart figure 9 (first part) cont'd n y y 3ch overdrive skip ? 69h overdrive match ? bit 0 match ? bit 1 match ? bit 63 match ? n n n y master tx bit 63 n od=1 od=1 master tx bit 0 master tx bit 1 y 3) 3) 3) to figure 9 first part from figure 9 first part from figure 9 first part y master tx reset pulse ? y n to figure 9 first part 3) always to be transmitted at overdrive speed
ds1962/DS1963 020698 17/22 1wire signaling the ds196x requires strict protocols to insure data integrity. the protocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1 and read data. all these signals except presence pulse are initiated by the bus master. the ds196x can communicate at two dif- ferent speeds, regular speed and overdrive speed. if not explicitly set into the overdrive mode, the ds196x will communicate at regular speed. while in overdrive mode the fast timing applies to all wave forms. the initialization sequence required to begin any com- munication with the ds196x is shown in figure 10. a reset pulse followed by a presence pulse indicates the ds196x is ready to send or receive data given the cor- rect rom command and memory function command. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 m s at regular speed, 48 m s at overdrive speed). the bus master then releases the line and goes into receive mode (rx). the 1wire bus is pulled to a high state via the pullup resistor. after detecting the rising edge on the data pin, the ds196x waits (t pdh , 1560 m s at regular speed, 26 m s at overdrive speed) and then transmits the presence pulse (t pdl , 60240 m s at regular speed, 824 m s at overdrive speed). a reset pulse of 480 m s or longer will exit the overdrive mode returning the device to regular speed. if the ds196x is in overdrive mode and the reset pulse is no longer than 80 m s the device will remain in overdrive mode. read/write time slots the definitions of write and read time slots are illustrated in figure 11. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the ds196x to the master by triggering a delay circuit in the ds196x. during write time slots, the delay circuit determines when the ds196x will sample the data line. for a read data time slot, if a a0o is to be transmitted, the delay circuit determines how long the ds196x will hold the data line low overriding the 1 gen- erated by the master. if the data bit is a a1o, the device will leave the read data time slot unchanged. initialization procedure areset and presence pluseso figure 10 t rsth t rstl t r v pullup v pullup min v ih min v il max 0v regular speed 480 m s < t rstl < * 480 m s < t rsth < ** 15 m s < t pdh < 60 m s 60 m s < t pdl < 240 m s t pdh t pdl master r x apresence pulseo master t x areset pulseo resistor master ds196x overdrive speed 48 m s < t rstl < 80 m s 48 m s < t rsth < ** 2 m s < t pdh < 6 m s 8 m s < t pdl < 24 m s *in order not to mask interrupt signaling by other devices on the 1wire bus, t rstl +t r should always be less than 960 m s **includes recovery time
ds1962/DS1963 020698 18/22 read/write time diagram figure 11 writeone time slot 60 m s t rec t low1 v pullup v pullup min v ih min v il max 0v regular speed 60 m s < t slot < 120 m s 1 m s < t low1 < 15 m s 1 m s < t rec < 15 m s ds196x sampling window t slot overdrive speed 6 m s < t slot < 16 m s 1 m s < t low1 < 2 m s 1 m s < t rec < (od: 2 m s) (od: 6 m s) writezero time slot v pullup v pullup min v ih min v il max 0v t slot t rec t low0 regular speed 60 m s < t low0 < t slot < 120 m s 1 m s < t rec < ds196x sampling window 60 m s 15 m s overdrive speed 6 m s < t low0 < t slot < 16 m s 1 m s < t rec < (od: 2 m s) (od: 6 m s) resistor master
ds1962/DS1963 020698 19/22 read/write timing diagram figure 11 cont'd readdata time slot v pullup v pullup min v ih min v il max 0v t slot t rec t rdv t lowr regular speed 60 m s < t slot < 120 m s 1 m s < t lowr < 15 m s 0 < t release < 45 m s 1 m s < t rec < t rdv = 15 m s t su < 1 m s t release master sampling window resistor master ds196x overdrive speed 6 m s < t slot < 16 m s 1 m s < t lowr < 2 m s 0 < t release < 4 m s 1 m s < t rec < t rdv = 2 m s t su < 1 m s t su crc generation with the ds196x there are two different types of crcs (cyclic redundancy checks). one crc is an 8bit type and is stored in the most significant byte of the 64bit rom. the bus master can compute a crc value from the first 56 bits of the 64bit rom and compare it to the value stored within the ds196x to determine if the rom data has been received errorfree by the bus master. the equivalent polynomial function of this crc is: x 8 + x 5 + x 4 + 1. this 8bit crc is received in the true (noninverted) form when reading the rom of the ds196x. it is computed at the factory and lasered into the rom. the other crc is a 16bit type, generated according to the standardized crc16polynomial function x 16 + x 15 + x 2 + 1. this crc is used for error detection when reading data memory using the read memory + counter command and for fast verification of a data transfer when writing to the scratchpad. it is the same type of crc as is used with nv ram based i buttons for error detection within the i button extended file struc- ture. in contrast to the 8bit crc, the 16bit crc is always returned or sent in the complemented (inverted) form. a crcgenerator inside the ds196x chip (figure 12) will calculate a new 16bit crc as shown in the command flow chart of figure 7. the bus master compares the crc value read from the device to the one it calculates from the data and decides whether to continue with an operation or to reread the portion of the data with the crc error. with the initial pass through the read memory + counter flow chart the 16bit crc value is the result of shifting the command byte into the cleared crc gener- ator, followed by the two address bytes, the data bytes, value of the page write cycle counter and tamperdetect bits. subsequent passes through the read memory + counter flow chart will generate a 16bit crc that is the result of clearing the crc generator and then shifting in the data bytes, the value of the page write cycle counter and the tamperdetect bits. with the write scratchpad command the crc is gener- ated by first clearing the crc generator and then shift- ing in the command code, the target addresses ta1 and ta2 and all the data bytes. the ds196x will trans- mit this crc only if the data bytes written to the scratch- pad include scratchpad ending offset 1 1111b. the data may start at any location within the scratchpad. for more details on generating crc values including example implementations in both hardware and soft- ware, see the abook of ds19xx i button standardso.
ds1962/DS1963 020698 20/22 crc16 hardware description and polynomial figure 12 1st stage 2nd stage 3rd stage 4th stage 5th stage 6th stage 7th stage 8th stage x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 polynomial = x 16 + x 15 + x 2 + 1 9th stage 10th stage 11th stage 12th stage 13th stage 14th stage 15th stage 16th stage x 9 x 10 x 11 x 12 x 13 x 14 x 15 input data x 16 crc output
ds1962/DS1963 020698 21/22 physical specification size see mechanical drawing weight 3.3 grams humidity 90% rh at 50 c altitude 10,000 feet expected service life 10 years at 25 c safety meets ul#913 (4th edit.); intrinsically safe apparatus, approval under entity concept for use in class i, division 1, group a, b, c and d locations (application pending) absolute maximum ratings* voltage on any pin relative to ground 0.5v to +7.0v operating temperature 40 c to +70 c storage temperature 40 c to +70 c * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electricial characteristics (v pup =2.8v to 6.0v; 40 c to +70 c) parameter symbol min typ max units notes logic 1 v ih 2.2 v 1, 8 logic 0 v il 0.3 +0.8 v 1, 9 output logic low @4 ma v ol 0.4 v 1 output logic high v oh v pup 6.0 v 1, 2 input load current i l 5 m a 3 capacitance (t a = 25 c) parameter symbol min typ max units notes i/o (1wire) c in/out 100 800 pf 6 ac electrical characteristics regular speed (v pup =2.8v to 6.0v; 40 c to +70 c) parameter symbol min typ max units notes time slot t slot 60 120 m s write 1 low time t low1 1 15 m s write 0 low time t low0 60 120 m s read low time t lowr 1 15 m s read data valid t rdv exactly 15 m s release time t release 0 15 45 m s read data setup t su 1 m s 5 recovery time t rec 1 m s reset time high t rsth 480 m s 4 reset time low t rstl 480 m s 7 presence detect high t pdh 15 60 m s presence detect low t pdl 60 240 m s
ds1962/DS1963 020698 22/22 ac electrical characteristics overdrive speed (v pup =2.8v to 6.0v; 40 c to +70 c) parameter symbol min typ max units notes time slot t slot 6 16 m s write 1 low time t low1 1 2 m s write 0 low time t low0 6 16 m s read low time t lowr 1 2 m s read data valid t rdv exactly 2 m s release time t release 0 1.5 4 m s read data setup t su 1 m s 5 recovery time t rec 1 m s reset time high t rsth 48 m s 4 reset time low t rstl 48 80 m s presence detect high t pdhigh 2 6 m s presence detect low t pdlow 8 24 m s notes: 1. all voltages are referenced to ground. 2. v pup = external pullup voltage. 3. input load is to ground. 4. an additional reset or communication sequence cannot begin until the reset high time has expired. 5. read data setup time refers to the time the host must pull the 1wire bus low to read a bit. data is guaranteed to be valid within 1 m s of this falling edge. 6. capacitance on the data pin could be 800 pf when power is first applied. if a 5 k w resistor is used to pull up the data line to v pup , 5 m s after power has been applied the parasite capacitance will not affect normal communica- tions. 7. the reset low time (t rstl ) should be restricted to a maximum of 960 m s, to allow interrupt signaling, otherwise, it could mask or conceal interrupt pulses. 8. v ih is a function of the external pullup resistor and v pup . 9. under certain low voltage conditions v ilmax may have to be reduced to as much as 0.5v to always guarantee a presence pulse.

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